
`include "cpu_if.sv"
`include "sram_if.sv"

module test_top;
  parameter RAM_ADDR_WDTH = 8;
  parameter NUM_OF_SRAMS = 4;
  parameter simulation_cycle = 10;

  logic SystemClock;
  logic reset;
  reg   vga_frm_sync;
  reg   m00_axis_tready;
  reg   clk_25mhz;

  cpu_if cpuif (SystemClock);
  sram_if sramif0(SystemClock);
 
  cntrlr_tb tb();

  vga_dma_ip DUT(
      .s00_axi_aclk         ( cpu_if.clk                  ) ,
      .s00_axi_aresetn      ( ~reset                      ) ,
      .s00_axi_awaddr       ( cpu_if.s00_axi_awaddr       ) ,
      .s00_axi_awprot       ( cpu_if.s00_axi_awprot       ) ,
      .s00_axi_awvalid      ( cpu_if.s00_axi_awvalid      ) ,
      .s00_axi_awready      ( cpu_if.s00_axi_awready      ) ,
      .s00_axi_wdata        ( cpu_if.s00_axi_wdata        ) ,
      .s00_axi_wstrb        ( cpu_if.s00_axi_wstrb        ) ,
      .s00_axi_wvalid       ( cpu_if.s00_axi_wvalid       ) ,
      .s00_axi_wready       ( cpu_if.s00_axi_wready       ) ,
      .s00_axi_bresp        ( cpu_if.s00_axi_bresp        ) ,
      .s00_axi_bvalid       ( cpu_if.s00_axi_bvalid       ) ,
      .s00_axi_bready       ( cpu_if.s00_axi_bready       ) ,
      .s00_axi_araddr       ( cpu_if.s00_axi_araddr       ) ,
      .s00_axi_arprot       ( cpu_if.s00_axi_arprot       ) ,
      .s00_axi_arvalid      ( cpu_if.s00_axi_arvalid      ) ,
      .s00_axi_arready      ( cpu_if.s00_axi_arready      ) ,
      .s00_axi_rdata        ( cpu_if.s00_axi_rdata        ) ,
      .s00_axi_rresp        ( cpu_if.s00_axi_rresp        ) ,
      .s00_axi_rvalid       ( cpu_if.s00_axi_rvalid       ) ,
      .s00_axi_rready       ( cpu_if.s00_axi_rready       ) , 
 
      .m00_axi_aclk         ( sramif0.clk                  ) ,
      .m00_axi_aresetn      ( ~reset                       ) ,
      .m00_axi_awid         ( sramif0.m00_axi_awid         ) ,
      .m00_axi_awaddr       ( sramif0.m00_axi_awaddr       ) ,
      .m00_axi_awlen        ( sramif0.m00_axi_awlen        ) ,
      .m00_axi_awsize       ( sramif0.m00_axi_awsize       ) ,
      .m00_axi_awburst      ( sramif0.m00_axi_awburst      ) ,
      .m00_axi_awlock       ( sramif0.m00_axi_awlock       ) ,
      .m00_axi_awcache      ( sramif0.m00_axi_awcache      ) ,
      .m00_axi_awprot       ( sramif0.m00_axi_awprot       ) ,
      .m00_axi_awqos        ( sramif0.m00_axi_awqos        ) ,
      .m00_axi_awuser       ( sramif0.m00_axi_awuser       ) ,
      .m00_axi_awvalid      ( sramif0.m00_axi_awvalid      ) ,
      .m00_axi_awready      ( sramif0.m00_axi_awready      ) ,
      .m00_axi_wdata        ( sramif0.m00_axi_wdata        ) ,
      .m00_axi_wstrb        ( sramif0.m00_axi_wstrb        ) ,
      .m00_axi_wlast        ( sramif0.m00_axi_wlast        ) ,
      .m00_axi_wuser        ( sramif0.m00_axi_wuser        ) ,
      .m00_axi_wvalid       ( sramif0.m00_axi_wvalid       ) ,
      .m00_axi_wready       ( sramif0.m00_axi_wready       ) ,
      .m00_axi_bid          ( sramif0.m00_axi_bid          ) ,
      .m00_axi_bresp        ( sramif0.m00_axi_bresp        ) ,
      .m00_axi_buser        ( sramif0.m00_axi_buser        ) ,
      .m00_axi_bvalid       ( sramif0.m00_axi_bvalid       ) ,
      .m00_axi_bready       ( sramif0.m00_axi_bready       ) ,
      .m00_axi_arid         ( sramif0.m00_axi_arid         ) ,
      .m00_axi_araddr       ( sramif0.m00_axi_araddr       ) ,
      .m00_axi_arlen        ( sramif0.m00_axi_arlen        ) ,
      .m00_axi_arsize       ( sramif0.m00_axi_arsize       ) ,
      .m00_axi_arburst      ( sramif0.m00_axi_arburst      ) ,
      .m00_axi_arlock       ( sramif0.m00_axi_arlock       ) ,
      .m00_axi_arcache      ( sramif0.m00_axi_arcache      ) ,
      .m00_axi_arprot       ( sramif0.m00_axi_arprot       ) ,
      .m00_axi_arqos        ( sramif0.m00_axi_arqos        ) ,
      .m00_axi_aruser       ( sramif0.m00_axi_aruser       ) ,
      .m00_axi_arvalid      ( sramif0.m00_axi_arvalid      ) ,
      .m00_axi_arready      ( sramif0.m00_axi_arready      ) ,
      .m00_axi_rid          ( sramif0.m00_axi_rid          ) ,
      .m00_axi_rdata        ( sramif0.m00_axi_rdata        ) ,
      .m00_axi_rresp        ( sramif0.m00_axi_rresp        ) ,
      .m00_axi_rlast        ( sramif0.m00_axi_rlast        ) ,
      .m00_axi_ruser        ( sramif0.m00_axi_ruser        ) ,
      .m00_axi_rvalid       ( sramif0.m00_axi_rvalid       ) ,
      .m00_axi_rready       ( sramif0.m00_axi_rready       ) ,
  
      .clk_vga              ( clk_25mhz                    ) 
  );
//-----------------------------------------------------------------------------
// Clock generation logic.
//-----------------------------------------------------------------------------
  initial begin
    #11799100
    $finish();
  end
  
  initial begin
      clk_25mhz = 0;
      forever  #(20) clk_25mhz = ~clk_25mhz;   
  end
     
  initial begin
    vga_frm_sync = 0;
    forever begin
      #(simulation_cycle)  vga_frm_sync = 0;
      #(simulation_cycle)  vga_frm_sync = 1;
      #(simulation_cycle)  vga_frm_sync = 1;
      #(simulation_cycle)  vga_frm_sync = 1;
      #(simulation_cycle)  vga_frm_sync = 0;
      #(simulation_cycle*8000) ;
    end  
  end

  initial begin
    m00_axis_tready = 0;
    forever begin
        #(simulation_cycle*500) m00_axis_tready = {$urandom};
    end
  end


  initial begin
    SystemClock = 0;
    forever begin
      #(simulation_cycle/2)
        SystemClock = ~SystemClock;
    end
  end

  `ifdef ENABLE_WAVE
  initial begin
    $fsdbDumpfile("top.fsdb");
    $fsdbDumpvars();
  end  
  `else
  initial $vcdpluson;
  `endif
endmodule
